1. Field of Industrial Utilization
This invention relates to a nonvolatile semiconductor memory, particularly to an EPROM and an EEPROM including a nonvolatile memory circuit and, more particularly to a circuit construction of a nonvolatile semiconductor memory of the batch erasure type (hereinafter referred to as a flash memory).
The invention further relates particularly to a circuit construction concerning a sense amplifying (S/A) circuit, supply of a supply voltage, improvement in the reliability of a writing operation, and a high speed reading operation in a nonvolatile semiconductor memory.
2. Description of the Prior Art
FIG. 8 shows diagrammatically a structure of a cell used in a flash memory.
In this figure, indicated at V.sub.G is a gate terminal, at V.sub.D a drain terminal, at V.sub.S a source terminal, at 27 a control gate CG connected to the gate terminal V.sub.G, and at 25 a floating gate FG which is controlled by the potential of the control gate CG.
Further, indicated at 22 is a semiconductor substrate, e.g., a semiconductor substrate having P-type conductivity. On the semiconductor substrate 22 are mounted well portions 23, 24 made of semiconductor having N-type conductivity. The well portion 23 forms a drain while the well portion 24 forms a source. Indicated at 26, 28 are insulating films.
When data is read from the cell, 0 V is applied to the source terminal v.sub.S, a read voltage (normal supply voltage V.sub.CC) of 5 V is applied to the gate terminal V.sub.G, and a voltage of about 1 V is applied to the drain terminal V.sub.D. Then, it is discriminated whether the read data is "1" or "0" depending upon whether a current flows through the cell. On the other hand, when data is written in the cell, 0 V is applied to the source terminal V.sub.S, a write/erase voltage V.sub.PP of about 12 V is applied to the gate terminal V.sub.G, and a write drain voltage V.sub.W (lower than V.sub.PP) is applied to the drain terminal V.sub.D. Thereby, electrons are injected into the floating gate FG from a drain region (writing operation). Further, when the data is erased, the drain terminal V.sub.D is brought into an open state, and 0 V and the write/erase voltage V.sub.PP are applied to the gate terminal V.sub.G and the source terminal V.sub.S respectively. Thereby, the electrons are taken from the floating gate FG to a source region (erasing operation).
When the data is written, it is required to check whether the data is written sufficiently in the memory cell (write verification). Likewise, when the data is written, it is required to check whether the data is erased sufficiently from the memory cell (erase verification).
The write verification and erase verification are carried out so as to confirm whether the degree of writing and the degree of erasing have a sufficient margin for the read voltage, i.e., a variation range of the normal supply voltage V.sub.CC (5 V.+-.0.5 V). Generally, these verifications are carried out to confirm that an operation margin of about 0.5 V to 1.0 V is available for a voltage range of V.sub.CC. In this case, the verify voltage including the operation margin is 6 V to 6.5 V in the write verification, and 3.5 V to 4 V in the erase verification.
It is expected that the write verification and the erase verification can be accomplished easily if the verify voltage including the operation margin to be secured is applied to word lines (for example, word lines WL.sub.1 to WL.sub.m of the flash memory shown in FIG. 1), so that the sensitivity of the S/A circuit is same regardless of whether the voltage V.sub.CC or the verify voltage is applied as the supply voltage of the S/A circuit.
FIG. 9 shows a construction of a general S/A circuit used in the nonvolatile semiconductor memory such as an EPROM.
In this figure, indicated at V.sub.CC is a line of a supply voltage 5 V, and at V.sub.SS a line of a supply voltage 0 V. Between the power supply lines V.sub.CC and V.sub.SS are connected a p-channel transistor 11 and an n-channel transistor 12 in series. A gate of the transistor 11 is connected to power supply line V.sub.SS, while a gate of the transistor 12 is connected to a data line (i.e., a bit line). Between the power supply line V.sub.CC and the data line is connected an n-channel transistor 13 whose gate is connected to drains of the respective transistors 11, 12. Likewise, between the power supply line V.sub.CC and the data line are connected a p-channel transistor 14 and an n-channel transistor 15 in series. A gate of the transistor 14 is connected to the power supply line V.sub.SS, while a gate of the transistor 15 is connected to the drains of the respective transistors 11, 12. An output (data output) of the S/A circuit is taken from drains of the respective transistors 14, 15.
In this construction, when the data read from the memory cell is "1", i.e., when the level of the data line is "H", the transistor 12 is turned on and thereby a drain potential thereof is reduced to "L" level. Accordingly, the transistor 15 is cut off. Thus, the voltage of "H" level is output from the power supply line V.sub.CC through the transistor 14 (data output). In other words, the data having the same level as the read data is sensed. Conversely, when the data read from the memory cell is "0", the transistor 12 is cut off and the voltage of "H" level is fed from the power supply line V.sub.CC through the transistor 11 to the gate of the transistor 15 to turn the transistor 15 on. Thereupon, the level of a data output line is reduced to "L" (the data of "L" level is the same as the read data).
In this way, the transistor 15 is provided with a function of transmitting the level of the bit line to the data output line (bit line level adjustment), and the transistor 14 is provided with a function of discriminating the data of the memory cell according to the state (on/off) of the transistor 15.
In the construction of the conventional S/A circuit as described above, the sensitivity of the S/A circuit becomes dependent on the voltage V.sub.CC since the voltage V.sub.CC is used as a supply voltage, thus presenting the problem that an original object of the verification cannot be accomplished.
On the other hand, the desired object can be accomplished if the voltage V.sub.CC is replaced by the verify voltage. However, since all the power to be consumed by the S/A circuit must be supplied by the verify voltage, the size, i.e., the current supplying performance of a power supply circuit for supplying the verify voltage is disadvantageously required to be increased.
Further, in the case where the writing operation is carried out in such a manner that a current within a dead band of the sense amplifier is caused to flow through the cell transistor in the conventional nonvolatile semiconductor memory, the sense amplifier oscillates during the reading operation and the data cannot be read accurately. However, the inaccurate reading operation cannot be verified in the write verification, thus the conventional nonvolatile semiconductor memory has lacked the reliability of the written data.
Moreover, in recent years, a high speed operation has been aimed at. However, there is a limit in carrying out the data writing, data reading, and erasing operations at a high speed in the conventional nonvolatile semiconductor memory in terms of its circuit construction and software, thus realization of higher operations are earnestly demanded.